High speed digital logic systems frequently run in a coherent manner, that is, a clock signal is distributed throughout the system to control the timing of system operation. When such systems run at high speeds, timing skew can occur between the data and clock. Timing skew is a misalignment of the clock and data phases from the desired alignment. For example, data transitions are usually set to occur during a portion of the clock cycle displaced from the clock transitions by a predetermined amount .DELTA..phi.. This is to allow data switching to complete before a clock transition occurs so that there is no ambiguity in detection of the data transition and so that undesired metastable logic states do not occur. Clock or timing skew results in .DELTA..phi. being larger or smaller than desired. If left uncorrected, serious data transmission or data processing errors may occur.
Timing skew is particularly severe where data and clocks must be transmitted to different parts of the system over different distances and where the various parts of the system may be at different temperatures. Under these circumstances, the data and the local clock phases may be misaligned or vary with time or temperature in different ways in different parts of the system. The local clock is the clock signal present in the part of the system of interest and may be a distributed form of the system clock or a locally generated or regenerated clock or a clock produced in some other way that is coherent with the system clock.
Timing adjustments are used to compensate for skew. One way to correct for fixed skew is to measure the phase difference between the data and the local clock and then provide timing adjustments, for example, by means of different lengths of coaxial cable which equalize the propagation time. Such arrangements are costly and awkward. The cables are bulky and it is time consuming to test different portions of the system and trim the cables to the precise lengths that are needed. Also, such techniques are difficult to use over a broad range of frequencies and are unable to compensate for dynamic skew, that is, phase errors that change with time, temperature, etc. Dynamic phase skew is also referred to as "phase jitter".
In the past a variety of schemes have been developed to deal with dynamic skew. For example, Cordell describes a digital phase aligner in U.S. Pat. No. 4,756,011 and in a related article entitled, "A 45-M bit/s CMOS-VLSI digital phase aligner", IEEE Journal of Solid State Circuits, Vol. 23, No. 2, April 1988, pp.323-328. Cordell's arrangement is illustrated in FlG. 1.
Referring now to FIG. 1, prior art digital phase aligner (DPA) 10 comprises quartet sampler 12, increment-decrement controller 14 and bi-phase register and multiplexer 16. The detailed description and operation of Cordell's DPA 10 is described in detail in U.S. Pat. No. 4,756,011 which is incorporated herein by reference, and the related article cited above and will only be summarized here.
DPA 10 receives at input 18 to sampler 12, data D having variable phase alignment with respect to local reference clock .phi.(0) to which it is desired to be aligned. DPA 10 provides at data output 19 from register-multiplexer 16, aligned data D.sub.out. Quartet sampler 12 receives multi-phase quadrature clock signals .phi.(0), .phi.(90), .phi.(180), .phi.(270) at inputs 20-23, where the numbers in parentheses indicate the relative phase of the clock signals supplied at inputs 20-23. Reference clock phase .phi.(0) is also supplied to controller 14 and register-multiplexer 16 at inputs 24, 26, respectively. Data D is propagated through sampler 12 and controller 14 to register-multiplexer 16. Data D is referred to as the "in-phase" data, that is, the data corresponding to clock phase .phi.(0). Data DA generated within sampler 12 is referred to as the "anti-phase" or "bi-phase" data, that is, the data corresponding to bi-phase or half-bit clock phase .phi.(180). DA is also propagated through controller 14 to register-multiplexer 16.
The operation of DPA 10 depends upon the fact that if a transition of data D is close to a clock transition and therefore not properly aligned, then the transition of DA will be far from a clock transition and will be aligned, and vice versa. DPA 10 automatically chooses between in-phase data D or anti-phase data DA so that the output data stream D.sub.out is aligned, i.e., the transitions of data stream D.sub.out are substantially stable with no bit errors due to misalignment.
Prior art DPA 10 uses a quadrature data sampling arrangement. Quartet sampler 12 detects whether a transition of data D occurs during quadrature phase intervals .phi.(0)-.phi.(90), .phi.(90)-.phi.(180), .phi.(180)-.phi.(270), or .phi.(270)-.phi.(0), and generates an "interference" output W, X, Y or Z identifying the respective quadrature phase interval during which the transition occurs. Sampler 12 provides interference signals W, X, Y, Z at outputs 30,31,32,33, in-phase data D at output 36 and anti-phase data DA at output 38.
Controller 14 propagates data D and DA to outputs 36',38' leading to register-multiplexer 16. Controller 14 decodes interference signals W,X,Y,Z to produce increment signal "UP" at output 40 or decrement signal "DN" at output 42 which, respectively, increment or decrement register-multiplexer 16 to transfer either data D or DA to aligned data output 19. Register-multiplexer 16 returns to controller 14, least-significant-bit signal LSB at output 46 so that controller 14 can know the current data state being transferred to aligned data output 19, i.e., either data D or DA.
DPA 10 operates according to the simplified truth-table shown in FIG. 2, where for different disagreement outputs W,X,Y,Z and different current data sample states (D or DA), the LSB state and multiplexer action are indicated. For example, if disagreement W from sampler 12 indicates that the current data transition occurs in first phase quadrant .phi.(0)-.phi.(90), and if the previous data sample caused register-multiplexer 16 to have selected in-phase data D for delivery to aligned data output 19, then the LSB counter provides a "1" and register-multiplexer 16 changes aligned output 19 to anti-phase data DA. Conversely, if the previous data sample caused register-multiplexer 16 to have selected anti-phase data DA, then LSB is a "0" and register-multiplexer 16 remains unchanged so that data DA continues to be coupled to aligned data output 19. A similar analysis applies to the disagreements signals X,Y,Z.
A difficulty with prior art arrangement 10 is that it requires quadrature clocks which are difficult to generate, particularly as the operating frequency increases. Cordell has described an improved version in U.S. Pat. No. 4,821,296 which is also incorporated herein by reference. It replaces quartet sampler 12 with a sextet sampler in which two primary bi-phase samples (i.e., at .phi.(0) and .phi.(180)) are used, each preceded and followed by two pairs of out-rigger samples for a total of six samples per clock period. The out-rigger samples are generated by a pair of two-stage delay circuits employing brief delays produced by inverters or other ordinary delay circuits which need not be precise phase increments, i.e., need not be ninety degree delays. With this arrangement, quadrature clocks are not needed.
However, Cordell's improved version still requires bi-phase (.phi.(0) and .phi.(180)) clocks with their associated out-riggers. The bi-phase clocks sample the data stream twice each clock period to provide D and DA. Without this bi-phase sampling and its attendant out-riggers, Cordell's improved arrangement does not work. A difficulty is that, the requirement for the bi-phase clock limits the attainable system speed to substantially less than the inherent speed of the underlying IC technology. Cordell's data must be re-clocked using the zero-phase clock, and this results in a half-period clock cycle, thereby limiting the achievable clock rate to half that of the IC technology being employed. If the system speed is pushed closer to the inherent upper limit of the lC technology being used, it becomes impossible to reliably generate stable and reasonably accurate bi-phase clock timing that is immune to temperature and component variations. Hence, there is an ongoing need for DPA means and methods which avoid these and other limitations of the prior art.